{"id":6682,"date":"2021-10-10T08:32:10","date_gmt":"2021-10-10T08:32:10","guid":{"rendered":"https:\/\/assignmenttutors.net\/blog\/eee-120-simulation-lab-4-the-microprocessor\/"},"modified":"2021-10-10T08:32:10","modified_gmt":"2021-10-10T08:32:10","slug":"eee-120-simulation-lab-4-the-microprocessor","status":"publish","type":"post","link":"https:\/\/assignmenttutors.net\/blog\/eee-120-simulation-lab-4-the-microprocessor\/","title":{"rendered":"Eee 120 simulation lab 4 – the microprocessor"},"content":{"rendered":"
\n

Task 4-1: Build the Brainless Central Processing Unit<\/span><\/strong><\/p>\n

Include a picture of your Logisim Brainless Central Processing Unit circuit here:<\/span><\/p>\n

Figure 1. Brainless Central Processing Unit JCC<\/span><\/p>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-2: Test and Control the Brainless Central Processing Unit<\/span><\/strong><\/p>\n

Perform the testing procedures outlined in the laboratory manual and fill in the blanks below. (Note that these questions appear in the text of the laboratory manual.)<\/span><\/p>\n

\u00b7 Record the first number placed on the data bus here: 5<\/span><\/p>\n

\u00b7 What do the following three switches need to be set to in order to perform the pass-through operation? \/~A_Only = 0 \/~Invert= 1 Logic\/~Arith= 0<\/span><\/p>\n

\u00b7 Enter the second number you entered into the data bus here: 2<\/span><\/p>\n

\u00b7 What do the following three switches need to be set to in order to perform the ADD operation? \/~A_Only = 1 \/~Invert= 1 Logic\/~Arith= 0<\/span><\/p>\n

\u00b7 Write down the number that appears in the accumulator here: 7<\/span><\/p>\n

Describe other numerical additions and other operations you checked in order to verify your brainless CPU here: I repeated the additions several times using 3, 4 and 1 and toggled through several times till I got the correct addition.<\/span><\/p>\n

After you are convinced your circuit is working properly, remove the 4-bit binary keyboard and set the\u00a0ACC to Data Bus<\/span><\/em>\u00a0pin to 1. Did the output of the accumulator appear on the data bus? Yes.<\/span><\/p>\n

How does the output of the ALU change? It changed to Hex E.<\/span><\/p>\n

If the 4-bit binary keyboard was not removed and the\u00a0ACC to Data Bus<\/span><\/em>\u00a0switch is set to 1, what would you expect to see displayed in the hex digit display attached to the data bus?<\/span><\/p>\n

I expect to see whatever is supplied to the data bus in hex display.<\/span><\/p>\n

Add the 4-bit binary keyboard back into your circuit and observe the hex digit display on the data bus for various keyboard values. Is the value on the hex digit display what you expected? Yes.<\/span><\/p>\n

Explain Only 1 signal is being allowed to enter the buffer at a time. Therefore, the buffer is receiving only the output of the register.<\/span><\/p>\n

Why do you think the register at the output of the ALU is called the \u2018accumulator\u2019? Because it stores data that passes through the ALU, it provides a feedback path tho the B input of the ALU and because it can store intermediate arithmetic or logic results.<\/span><\/p>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-3: Build the Addressing Logic<\/span><\/strong><\/p>\n

Include a picture of your Logisim addressing logic circuit here:<\/span><\/p>\n

Figure 2. Addressing Logic JCC<\/span><\/p>\n

Test your circuit and record the results in\u00a0Table 1<\/span><\/strong>. Include a picture of your Logisim addressing logic circuit testing set up.<\/span><\/p>\n

Figure 3. Testing Addressing Logic JCC<\/span><\/p>\n\n\n\n\n\n\n\n\n
\n

Table 1<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

A<\/span><\/p>\n

(4-bit binary)<\/span><\/p>\n<\/td>\n

\n

Y0<\/span><\/p>\n<\/td>\n

\n

Y1<\/span><\/p>\n<\/td>\n

\n

Y2<\/span><\/p>\n<\/td>\n

\n

Y3<\/span><\/p>\n<\/td>\n

\n

Y4<\/span><\/p>\n<\/td>\n

\n

Y5<\/span><\/p>\n<\/td>\n

\n

Y6<\/span><\/p>\n<\/td>\n

\n

Y7<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0000<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0001<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0010<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0011<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-4: Build a 4-Bit ROM Memory Cell<\/span><\/strong><\/p>\n

Include a picture of your Logisim 4-bit ROM circuit here:<\/span><\/p>\n

Figure 4. 4-bit ROM memory cell JCC<\/span><\/p>\n

Test your circuit and record the results in\u00a0Table 2<\/span><\/strong>. Include a picture of your Logisim 4-bit ROM circuit testing set up.<\/span><\/p>\n

Figure 5. Testing 4-bit ROM memory cell JCC<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n
\n

Table 2<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

A<\/span><\/p>\n

(4-bit binary)<\/span><\/p>\n<\/td>\n

\n

Read<\/span><\/p>\n<\/td>\n

\n

Memory Select<\/span><\/p>\n<\/td>\n

\n

Y<\/span><\/p>\n

(Data Bus)<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0001<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0101<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

1000<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

8<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

1000<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

X<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

1000<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

X<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

1000<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

X<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-5: Build 4-Bit Output Port<\/span><\/strong><\/p>\n

Include a picture of your Logisim 4-bit output port circuit here:<\/span><\/p>\n

Figure 6. 4-bit output device JCC<\/span><\/p>\n

Test your circuit and record the results in\u00a0Table 3<\/span><\/strong>.<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Table3<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Data Bus (4-bit binary)<\/span><\/p>\n<\/td>\n

\n

Write<\/span><\/p>\n<\/td>\n

\n

Memory Select<\/span><\/p>\n<\/td>\n

\n

Q<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0001<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0010<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

Last Q<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0011<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

Last Q<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0011<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

Last Q<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0011<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0011<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0011<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0001<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-6: Build the 4-Bit RAM Cell<\/span><\/strong><\/p>\n

Include a picture of your Logisim 4-bit RAM circuit here:<\/span><\/p>\n

Figure 7. 4-bit RAM JCC<\/span><\/p>\n

Test your circuit and record the results in\u00a0Table 4<\/span><\/strong>. Include a picture of your Logisim 4-bit RAM circuit testing set up.<\/span><\/p>\n

Figure 8. Testing 4-bit RAM JCC<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n
\n

Table4<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Data Bus<\/span><\/p>\n

(4-bit binary)<\/span><\/p>\n<\/td>\n

\n

Write<\/span><\/p>\n<\/td>\n

\n

Memory Select<\/span><\/p>\n<\/td>\n

\n

Read<\/span><\/p>\n<\/td>\n

\n

Q {between register and buffer}<\/span><\/p>\n<\/td>\n

\n

Data Bus {after buffer}<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0110<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0110<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0110<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n

\n

–<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0110<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n

\n

–<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0110<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n

\n

–<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0101<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-7: Build the Brainless Microprocessor<\/span><\/strong><\/p>\n

Include a picture of your Logisim brainless microprocessor circuit here:<\/span><\/p>\n

\u00a0<\/span><\/p>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-8: Testing and Controlling the Brainless Microprocessor<\/span><\/strong><\/p>\n

Follow steps 1 through 3 outlined in the laboratory manual to test your brainless microprocessor circuit. List in Table 5 <\/span><\/strong>the control lines you needed to control to\u00a0store the accumulator (ACC) to <\/span><\/strong><\/span><\/p>\n

\u00a0<\/span><\/strong><\/p>\n

RAM<\/span><\/strong>. (If the control line value has no impact, place a dash \u2018-\u2018 in the value column).<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Table5<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Control line<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

4-bit binary keyboard<\/span><\/p>\n

(Address Bus)<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Write<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Read<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~A_Only<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Describe any other tests that you performed. NOTE: the laboratory manual gives you a minimum set of items to test: __________________________________________________________________________<\/span><\/p>\n

_____________________________________________________________________________________<\/span><\/p>\n

___________________________________________________________________________________<\/span><\/p>\n

____________________________________________________________________________________<\/span><\/p>\n

____________________________________________________________________________________<\/span><\/p>\n

\u00a0<\/span><\/p>\n

\u00a0<\/span><\/strong><\/p>\n

Table 6 <\/span><\/strong>is an example, for the ADD command, of how to fill out tables to record the values of the control lines during every clock cycle.<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Table6<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Instruction [ Add operand to Accumulator (ACC) ]<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Control Line<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

4-bit Binary Keyboard (Address Bus)<\/span><\/p>\n<\/td>\n

\n

Address of operand<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Write<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Read<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~A_Only<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

For all of the instructions you performed (i.e. Subtract, Load ACC, etc.) record the values of the control lines during every clock cycle in\u00a0Table 7<\/span><\/strong>,\u00a0Table 8<\/span><\/strong>and\u00a0Table 9<\/span><\/strong>.<\/span><\/p>\n

\u00a0<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Table7<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Instruction [Subtract operand from ACC ]<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Control Line<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

4-bit Binary Keyboard (Address Bus)<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Write<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Read<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~A_Only<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Table8<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Instruction [Load ACC with operand]<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Control Line<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

4-bit Binary Keyboard (Address Bus)<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Write<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Read<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~A_Only<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n<\/tr>\n
\n

Instruction[AND operand with ACC]<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Control Line<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

4-bit Binary Keyboard (Address Bus)<\/span><\/p>\n<\/td>\n

\n

x<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Write<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Read<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~A_Only<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n<\/tr>\n
\n

Instruction[ Store ACC to RAM]<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Control Line<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

4-bit Binary Keyboard (Address Bus)<\/span><\/p>\n<\/td>\n

\n

X<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Write<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Read<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~A_Only<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Table 9<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Instruction[ Not (operand) to ACC]<\/span><\/strong><\/p>\n

(1\u2019s complement)<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Control Line<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

4-bit Binary Keyboard (Address Bus)<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Write<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Read<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~A_Only<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n<\/tr>\n
\n

Instruction[ Negate(operand) to ACC]<\/span><\/strong><\/p>\n

(2\u2019s complement)<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Control Line<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

4-bit Binary Keyboard (Address Bus)<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Write<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Read<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~A_Only<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-9: Build the Memory-Address-Generation Circuit<\/span><\/strong><\/p>\n

Include a picture of your Logisim memory address generation circuit here:<\/span><\/p>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-10: Build the Controller Circuit<\/span><\/strong><\/p>\n

Include a picture of your Logisim controller circuit here:<\/span><\/p>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-11: Build the Complete Microprocessor Circuit<\/span><\/strong><\/p>\n

Include a picture of your Logisim complete microprocessor circuit, with controller, here:<\/span><\/p>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-12: Write and Execute a Simple Program for Your Microprocessor<\/span><\/strong><\/p>\n

Write the program given in your laboratory manual into the appropriate memory locations. Observe the operation of each step of your program (i.e. observe the values of the control lines and record whether data is being moved properly according to those control line settings). Did you get an 8 stored into the accumulator with you initial test?______<\/span><\/p>\n

If not, what error(s) did you find during your debugging process?________________________________<\/span><\/p>\n

_____________________________________________________________________________________<\/span><\/p>\n

_____________________________________________________________________________________<\/span><\/p>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-13: Add the \u2018AND\u2019, \u2018Zero\u2019, \u2018Subtract\u2019, and \u2018Store ACC\u2019 Instructions<\/span><\/strong><\/p>\n

\u00a0<\/span><\/p>\n

Use\u00a0Table 10<\/span><\/strong>and\u00a0Table 11<\/span><\/strong>to enter your values into the microinstruction definition table for each of the four instructions asked for in the laboratory manual. Be sure to label the name of each and every instruction.<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Table10<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n\n

Instruction<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\n

Opcode<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n

\n

4<\/span><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n\n

Pres. State<\/span><\/p>\n<\/td>\n

\n

00<\/span><\/p>\n<\/td>\n

\n

01<\/span><\/p>\n<\/td>\n

\n

02<\/span><\/p>\n<\/td>\n

\n

03<\/span><\/p>\n<\/td>\n

\n

00<\/span><\/p>\n<\/td>\n

\n

01<\/span><\/p>\n<\/td>\n

\n

02<\/span><\/p>\n<\/td>\n

\n

03<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Description<\/span><\/strong><\/p>\n<\/td>\n

\n

Pin number<\/span><\/strong><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Next State Bits<\/span><\/p>\n<\/td>\n

\n

1-0<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Load IR<\/span><\/p>\n<\/td>\n

\n

2<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Write<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Read<\/span><\/p>\n<\/td>\n

\n

4<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Load MAR<\/span><\/p>\n<\/td>\n

\n

7<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Use PC<\/span><\/p>\n<\/td>\n

\n

8<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

\/~A_only<\/span><\/p>\n<\/td>\n

\n

9<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

10<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

11<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

12<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

13<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

14<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

15<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\n

HEX equiv<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Table11<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n\n

Instruction<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\n

Opcode<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n\n

Pres. State<\/span><\/p>\n<\/td>\n

\n

00<\/span><\/p>\n<\/td>\n

\n

01<\/span><\/p>\n<\/td>\n

\n

02<\/span><\/p>\n<\/td>\n

\n

03<\/span><\/p>\n<\/td>\n

\n

00<\/span><\/p>\n<\/td>\n

\n

01<\/span><\/p>\n<\/td>\n

\n

02<\/span><\/p>\n<\/td>\n

\n

03<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Description<\/span><\/strong><\/p>\n<\/td>\n

\n

Pin number<\/span><\/strong><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Next State Bits<\/span><\/p>\n<\/td>\n

\n

1-0<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Load IR<\/span><\/p>\n<\/td>\n

\n

2<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Write<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Read<\/span><\/p>\n<\/td>\n

\n

4<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Load MAR<\/span><\/p>\n<\/td>\n

\n

7<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Use PC<\/span><\/p>\n<\/td>\n

\n

8<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

\/~A_only<\/span><\/p>\n<\/td>\n

\n

9<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

10<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

11<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

12<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

13<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

14<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

15<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\n

HEX equiv<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Test your instructions by writing and executing programs. Record at least\u00a0four<\/span><\/strong>\u00a0programs and the output of each program in tables like that of\u00a0Table 12<\/span><\/strong>.<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Table12<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Program #0 (\u00a0Example<\/span><\/em>: ADD = 3+5)<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Address<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n

\n

Operation (In English)<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

0<\/span><\/p>\n<\/td>\n

\n

The ‘Load ACC’ Opcode<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n

\n

The number ‘3’ to be loaded into the Accumulator<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

2<\/span><\/p>\n<\/td>\n

\n

1<\/span><\/p>\n<\/td>\n

\n

The ‘Add to ACC’ Opcode<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

3<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n

\n

The number ‘5’ to be added to the Accumulator<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

4<\/span><\/p>\n<\/td>\n

\n

2<\/span><\/p>\n<\/td>\n

\n

The ‘Stop’ Opcode<\/span><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

What was the final output of your program? ___8__<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Was the program successful? YES_<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

If not what error(s) did you find in your circuit?<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Program # ( )<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Address<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n

\n

Operation (In English)<\/span><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

What was the final output of your program? _____<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Was the program successful? Yes or No_<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

If not what error(s) did you find in your circuit?<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/strong><\/p>\n

Task 4-14: Invent Your Own Instruction (Extra Credit)<\/span><\/strong><\/p>\n

Fill in the following two tables for your invented instruction.<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\u00a0<\/td>\n\n

Instruction<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\n

Opcode<\/span><\/p>\n<\/td>\n

\n

7<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\n

Pres. State<\/span><\/p>\n<\/td>\n

\n

00<\/span><\/p>\n<\/td>\n

\n

01<\/span><\/p>\n<\/td>\n

\n

02<\/span><\/p>\n<\/td>\n

\n

03<\/span><\/p>\n<\/td>\n

\n

00<\/span><\/p>\n<\/td>\n

\n

01<\/span><\/p>\n<\/td>\n

\n

02<\/span><\/p>\n<\/td>\n

\n

03<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Description<\/span><\/strong><\/p>\n<\/td>\n

\n

Pin number<\/span><\/strong><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Next State Bits<\/span><\/p>\n<\/td>\n

\n

1-0<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Load IR<\/span><\/p>\n<\/td>\n

\n

2<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Write<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Read<\/span><\/p>\n<\/td>\n

\n

4<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

ACC to Data Bus<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Load ACC<\/span><\/p>\n<\/td>\n

\n

6<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Load MAR<\/span><\/p>\n<\/td>\n

\n

7<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Use PC<\/span><\/p>\n<\/td>\n

\n

8<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

\/~A_only<\/span><\/p>\n<\/td>\n

\n

9<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

\/~Invert<\/span><\/p>\n<\/td>\n

\n

10<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Logic\/~Arith<\/span><\/p>\n<\/td>\n

\n

11<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

12<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

13<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

14<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

X<\/span><\/p>\n<\/td>\n

\n

15<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\n

HEX equiv<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Program # ( )<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Address<\/span><\/p>\n<\/td>\n

\n

Value<\/span><\/p>\n<\/td>\n

\n

Operation (In English)<\/span><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

What was the final output of your program? _____<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

Was the program successful? Yes or No_<\/span><\/p>\n<\/td>\n<\/tr>\n

\n

If not what error(s) did you find in your circuit?<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Simulation Lab 4: Lab Report Grade Sheet<\/span><\/p>\n

Instructor Assessment: Task Oriented<\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Grading Criteria<\/span><\/strong><\/p>\n<\/td>\n

\n

MaxPoints<\/span><\/strong><\/p>\n<\/td>\n

\n

Points Lost<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n

\n

Template<\/span><\/strong><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Neatness, Clarity, and Concision<\/span><\/p>\n<\/td>\n

\n

2<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Description of Assigned Tasks, Work Performed & Outcomes Met<\/span><\/strong><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Task 4-1: Build the Brainless Central Processing Unit<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-2: Test and Control the Brainless Central Processing Unit<\/span><\/p>\n<\/td>\n

\n

12<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-3: Build the Addressing Logic<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-4: Build a 4-Bit ROM Memory Cell<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-5: Build 4-Bit Output Port<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-6: Build the 4-Bit RAM Cell<\/span><\/p>\n<\/td>\n

\n

3<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-7: Build the Brainless Microprocessor<\/span><\/p>\n<\/td>\n

\n

10<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-8: Testing and Controlling the Brainless Microprocessor<\/span><\/p>\n<\/td>\n

\n

14<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-9: Build the Memory-Address-Generation Circuit<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-10: Build the Controller Circuit<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-11: Build the Complete Microprocessor Circuit<\/span><\/p>\n<\/td>\n

\n

10<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-12: Write and Execute a Simple Program for your Microprocessor<\/span><\/p>\n<\/td>\n

\n

5<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-13: Add the \u2018AND\u2019, \u2018Zero\u2019, \u2018Subtract\u2019, and \u2018Store ACC\u2019 Instructions<\/span><\/p>\n<\/td>\n

\n

20<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Task 4-14: Invent Your Own Instruction<\/span><\/p>\n<\/td>\n

\n

(5 extra points)<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Self-Assessment Worksheet\u00a0<\/span><\/strong>(The content of the self-assessment worksheet will not be graded. Full credit is given for including the completed worksheet.)<\/span><\/p>\n<\/td>\n

\n

(2 extra points)<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\n

Points Lost<\/span><\/strong><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\n

Lab Score<\/span><\/p>\n<\/td>\n

\n

Late Lab<\/span><\/strong><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n
\u00a0<\/td>\n\n

Lab Score<\/span><\/strong><\/p>\n<\/td>\n

\u00a0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Self-Assessment Worksheet<\/span><\/p>\n

Put \u2018X\u2019s\u2019 in the table below indicating how strongly you agree or disagree that the outcomes of the assigned tasks were achieved. Use \u20185\u2019 to indicate that you \u2018strongly agree\u2019, \u20183\u2019 to indicate that you are ‘neutral’, and \u20181\u2019 to indicate that you \u2018strongly disagree\u2019. Use \u2018NA\u2019, \u2018Not Applicable\u2019, when the tasks you performed did not elicit this outcome. Credit will be given for including this worksheet with your lab report; however, your\u00a0responses<\/span><\/strong>\u00a0will not be graded<\/span><\/strong>. They are for your instructor\u2019s information only.<\/span><\/p>\n

\u00a0<\/span><\/strong><\/p>\n

Table 14: Self-Assessment of Outcomes for Simulation Lab 4: The Brainless Microprocessor<\/span><\/strong><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

After completing the assigned tasks and report, I am able to:<\/span><\/strong><\/p>\n<\/td>\n

\n

5<\/span><\/strong><\/p>\n<\/td>\n

\n

4<\/span><\/strong><\/p>\n<\/td>\n

\n

3<\/span><\/strong><\/p>\n<\/td>\n

\n

2<\/span><\/strong><\/p>\n<\/td>\n

\n

1<\/span><\/strong><\/p>\n<\/td>\n

\n

NA<\/span><\/strong><\/p>\n<\/td>\n<\/tr>\n<\/thead>\n

\n

Build, debug and control a simulation of a central processing unit (CPU)<\/span><\/p>\n<\/td>\n

\n

X<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Build, debug and control a simulation of a ROM, RAM and an output port.<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\n

X<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Build and debug a simulation of a microprocessor that is absent a controller.<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\n

X<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Act as the controller for an elementary microprocessor.<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\n

X<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Design a PROM-based controller for an elementary microprocessor.<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\n

X<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Create an instruction set for an elementary microprocessor.<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\n

X<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Use the language of your instruction set to create a program and enter it into memory.<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\n

X<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n
\n

Execute a program on your simulated microprocessor.<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\n

X<\/span><\/p>\n<\/td>\n

\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Write below any suggestions you have for improving this laboratory exercise so that the stated learning outcomes are achieved.<\/span><\/p>\n

\u00a0<\/p>\n

\u00a0<\/span><\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

Task 4-1: Build the Brainless Central Processing Unit Include a picture of your Logisim Brainless Central Processing Unit circuit here: Figure 1. Brainless Central Processing Unit JCC \u00a0 Task 4-2: Test and Control the Brainless Central Processing Unit Perform the testing procedures outlined in the laboratory manual and fill in the blanks below. (Note that […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[31],"tags":[],"class_list":["post-6682","post","type-post","status-publish","format-standard","hentry","category-homework-help"],"_links":{"self":[{"href":"https:\/\/assignmenttutors.net\/blog\/wp-json\/wp\/v2\/posts\/6682","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/assignmenttutors.net\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/assignmenttutors.net\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/assignmenttutors.net\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/assignmenttutors.net\/blog\/wp-json\/wp\/v2\/comments?post=6682"}],"version-history":[{"count":0,"href":"https:\/\/assignmenttutors.net\/blog\/wp-json\/wp\/v2\/posts\/6682\/revisions"}],"wp:attachment":[{"href":"https:\/\/assignmenttutors.net\/blog\/wp-json\/wp\/v2\/media?parent=6682"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/assignmenttutors.net\/blog\/wp-json\/wp\/v2\/categories?post=6682"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/assignmenttutors.net\/blog\/wp-json\/wp\/v2\/tags?post=6682"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}